Integrated circuits (abbreviated IC) are widely used in the implementation of various electronic devices. In a number of applications, for example in mobile stations or other battery-operated compact and portable devices, the power consumption of integrated circuits contained in the devices is a very essential factor to be considered in the design and implementation of the devices. Low power consumption makes e.g. longer operating times possible without increasing the physical size of the devices.
In ASIC circuits, as well as in other integrated circuits, the power consumption can be either static or dynamic in nature. In this context, static power consumption refers to the power consumption of the circuit in a situation, in which the circuit is in the idle state, not executing any actual functions but with the operating voltage turned on. In a corresponding manner, dynamic power consumption refers to the power consumption when the circuit is executing its functions. The quantity of dynamic power consumption varies according to the functions executed by the circuit at the time.
The static power consumption of ASIC circuits is largely determined by the processing technique used in the manufacture of the circuits, and thus it cannot be significantly influenced by the design of the functionality of the circuits. In circuit designing, determining the functions to be included in the ASIC circuit being designed, it is, however, possible to significantly influence the dynamic power consumption of the circuit. In principle, the most important factors on the power consumption of the ASIC circuit are the capacitance, the operating voltage, and the clock frequency of the circuit. In the design, the capacitance is determined e.g. on the basis of the surface areas of the components to be implemented on the circuit, and the capacitance of the circuit cannot be influenced at a later stage during the actual use of the circuit. However, the operating voltage and the clock frequency of the circuit can also be changed during the use, wherein it is further possible to affect the dynamic power consumption of the circuit. It is thus an aim of the present invention to control these last-mentioned parameters as effectively as possible, to minimize the dynamic power consumption of the circuit in different use situations.
U.S. Pat. No. 5,910,930 describes a solution for dynamic power control to minimize the power consumption in a microprocessor which comprises several hardware units with different functions. According to U.S. Pat. No. 5,910,930 and the appended FIG. 1, each of said hardware units 107 involves, as an input, a clock and control signal 103 and, as an output, a powered-down mode enable signal 104. The operation of the hardware units 107, utilizing said signals, is controlled by a clock and power management subsystem 100 included in the microprocessor and comprising a clock generation and control logic 101 and a powered-down mode register 102.
When a given hardware unit 107 activates its powered-down mode enable signal 104, the clock and power management subsystem 100 is thus informed that said hardware unit 107 is ready for the transfer to the powered-down mode. By using signals 105, 106, a register control logic 109 stores information in the powered-down mode register 102 about the type of powered-down mode in which the hardware unit 107 can be transferred. The clock generation and control logic 101 will now combine the information included in the signals 104 and 108 and transfer, by means of the clock and control signal 103, said hardware unit 107 to the suitable powered-down mode. In other words, the clock signal to be transferred to the hardware unit 107 is run down, or the frequency of the clock signal is suitably lowered. When the hardware unit 107 informs, by changing the state of the powered-down mode enable signal 104, the management subsystem 101 about its need to restore the normal mode, the control logic 101 will reset the clock signal to be transferred to the hardware unit 107 to normal. If the hardware unit 107 needs to re-enter the powered-down mode defined in the powered-down mode register 102, this will be effected by reactivating the powered-down mode enable signal 104.
The advantages of the solution presented in U.S. Pat. No. 5,910,930 are based on the fact that the hardware unit 107 can quickly enter or leave the powered-down mode simply by changing the state of the powered-down mode enable signal 104. In other words, the clock generation and control logic 101 is implemented by means of logic circuits as a combination logic, wherein the operation of said unit 101 is fast and does not require software operations.
In prior art, there are also known solutions implemented by software and based on so-called state machines, in which information about the states of different hardware units and also the decision on directing the different hardware units to a suitable powered-down mode are processed by programming. However, state machines or the like, implemented by software, have the drawback that they must be allocated resources, such as a memory, on the integrated circuit. The use of state machines will also require that the processor unit belonging to the system is kept active, which increases the power consumption. Furthermore, the software processing and storage of powered-down modes allowed for the states and different hardware units in a system will significantly increase delays upon turning the powered-down mode on and off. This will cause problems particularly in such solutions in which schedules are designed to be critical so that the too late activation of a hardware unit from the powered-down mode to the operating mode, or vice versa, will interfere with other processes or hardware units in the system by causing delays or actual malfunctions.
The above-presented dynamic powered-down solutions of prior art have proven to be unsatisfactory, particularly in solutions requiring very aggressive power saving but still precisely predictable system response times. When using solutions of prior art, particularly in more complex systems comprising several hardware units, the delay times for “energizing” the system to operation from the powered-down mode to a standby mode are very difficult to predict under changing conditions, wherein, to be on the safe side, the system must be energized slightly in advance, before the moment when the system should be ready for operation at the latest. Thus, when the system is ready for operation but it does not yet execute any actual function, it unnecessarily consumes energy.
An example of such an application is a battery-operated mobile station, in which the mobile station should be able to continuously keep its power consumption as low as possible to maximize the operation time but at the same time, however, be synchronized with a base station to maintain readiness for operation.